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Integrated Circuit Systems, Inc.
ICS950202
Programmable Timing Control HubTM for P4TM
Recommended Application: CK-408 clock for Intel(R) 845 chipset. Output Features: * 3 - Pairs of differential CPU clocks @ 3.3V * 3 - 3V66 @ 3.3V * 9 - PCI @ 3.3V * 2 - 48MHz @ 3.3V fixed * 1 - VCH/3V66 @ 3.3V, 48MHz or 66MHz * 1 - REF @ 3.3V, 14.318MHz Features/Benefits: * Programmable output frequency. * Programmable output divider ratios. * Programmable output rise/fall time. * Programmable output skew. * Programmable spread percentage for EMI control. * Watchdog timer technology to reset system if system malfunctions. * Programmable watch dog safe frequency. * Support I2C Index read/write and block read/write operations. * Uses external 14.318MHz crystal. Key Specifications: * CPU Output Jitter <150ps * 3V66 Output Jitter <250ps * CPU Output Skew <100ps
VDDREF X1 X2 GND 1 **FS0/PCICLK7 1 **FS1/PCICLK8 VDDPCI GND 1 *WDEN/PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 VDD3V66 GND 3V66_1 3V66_2 3V66_3 #RESET VDDA
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF/FS2** CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 GND VDDCPU CPUCLKT2 CPUCLKC2 MULTISEL0* I REF GND 48MHz_USB/FS3** 48MHz_DOT AVDD48 GND 3V66_0/VCH_CLK/FS4** VDD3V66 GND SCLK SDATA Vtt_PWRGD/PD# GND
1
48-Pin 300-mil SSOP
1. These outputs have 2X drive strength. * Internal Pull-up resistor of 120K to VDD ** these inputs have 120K internal pull-down to GND
Block Diagram Frequency Table
FS4 FS3 FS2 FS1 FS0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 1 CPUCLK MHz 100.00 133.33 66.67 200.00 3V66 MHz 66.67 66.67 66.67 66.67 PCICLK MHz 33.33 33.33 33.34 33.33
For additional frequency selections please refer to Byte 0.
Power Groups
VDDA = Analog Core PLL VDDREF = REF, Xtal AVDD48 = 48MHz
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ICS950202
Integrated Circuit Systems, Inc.
ICS950202
General Description
The ICS950202 is a single chip clock solution for desktop designs using the Intel 845 chipset with PC133 or DDR memory. It provides all necessary clock signals for such a system. The ICS950202 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
P IN N U M B E R 1, 7, 13, 18, 30, 41, 45 2 3 4, 8, 14, 19, 25, 29, 32, 36, 42 22, 21, 20 5 VDD X1 X2 GND 3V 66 (3:1) P C IC LK 7 FS 0 PCICLK8 6 FS 1 9 WDEN P C IC LK 0 IN IN O UT O UT O UT P WR IN IN IN I/O OUT IN P WR O UT IN O UT O UT IN O UT O UT IN O UT Logi c i nput frequency select bi t. Input latched at power on. Hardware enable of watch dog circuit. Enabled when latched high. 3.3V P C I clock output. 3.3V P C I clock outputs. Real time system reset signal for frequency value or watchdog timmer timeout. This signal is active low. A nalog power 3.3V. This 3.3V LVTTL input is a level sensitive strobe used to determine when FS (4:0) inputs are valid and are ready to be sampled (active high). A synchronous acti ve low i nput pi n used to power down the devi ce i nto a low power state. The i nternal clocks are di sabled and the V C O and the crystal are stopped. The latency of the power down wi ll not be greater than 3ms. Clock pin for I2C circuitry 5V tolerant. Data pin for I2C circuitry 5V tolerant. 3.3V output selectable through I2C to be 66MHz from internal VCO or 48MHz (non-SSC). Logi c i nput frequency select bi t. Input latched at power on. A nalog power 3.3V. 3.3V F i xed 48MHz clock output for D OT. Logi c i nput frequency select bi t. Input latched at power on. 3.3V F i xed 48MHz clock output for US B . This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 3.3V LVTTL input for selecting the current multiplier for CPU outputs "Complementory" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. Logi c i nput frequency select bi t. Input latched at power on. 3.3V, 14.318MHz reference clock output. P I N N AM E T YP E P WR IN O UT P WR O UT O UT IN OUT 3.3V power supply. C rystal i nput, has i nternal load cap (33pF ) and feedback resi stor from X 2. C rystal output, nomi nally 14.318MHz. Has i nternal load cap (33pF ). Ground pi ns for 3.3V supply. 3.3V F i xed 66MHz clock outputs for HUB . 3.3V P C I clock output Logi c i nput frequency select bi t. Input latched at power on. 3.3V P C I clock output. D E S C R IP T ION
17, 16, 15, 12, 11, 10 P C IC LK (6:1) 23 24 RESET# VDDA Vtt_PWRGD 26 PD# 28 27 31 33 34 35 37 38 39, 43, 46 40, 44, 47 48 S C LK S D ATA 3V66_0/VCH_CLK FS 4 AV D D 48 48MHz_D OT FS3 48MHz_US B I REF MULTSEL0 CPUCLKC (2:0) CPUCLKT (2:0) FS 2 RE F
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Integrated Circuit Systems, Inc.
ICS950202
Maximum Allowed Current
Max 3.3V supply consumption Max discrete cap loads, Vdd = 3.465V All static inputs = Vdd or GND 40mA 360mA
Condition Powerdown Mode (PWRDWN# = 0) Full Active
Host Swing Select Functions
MULTISEL0 Board Target Trace/Term Z 50 ohms 50 ohms Reference R, Iref = VDD/(3*Rr) Rr = 221 1%, Iref = 5.00mA Rr = 475 1%, Iref = 2.32mA Output Current Ioh = 4* I REF Ioh = 6* I REF Voh @ Z
0 1
1.0V @ 50 0.7V @ 50
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Integrated Circuit Systems, Inc.
ICS950202
General I2C serial interface information How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
T Controller (Host) starT bit ICS (Slave/Receiver) Slave Address D2(H) WRite WR ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte
Index Block Read Operation
T Controller (Host) starT bit ICS (Slave/Receiver) Slave Address D2(H) WR WRite ACK Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte Byte N + X - 1 N P Not acknowledge stoP bit
Byte N + X - 1 ACK P stoP bit
*See notes on the following page.
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Integrated Circuit Systems, Inc.
ICS950202
Byte 0: Functionality and frequency select register (Default=0)
Bit Description Bit2 Bit7 Bit6 Bit5 Bit4 CPUCLK MHz FS4 FS3 FS2 FS1 FS0 3V66 MHz PCICLK MHz Spread % PWD
Bit (2,7:4)
Bit 3 Bit 1 Bit 0
0 0 0 0 0 100.90 67.27 33.63 +/-0.35% center spread 0 0 0 0 1 100.00 66.67 33.33 0 to -0.6% down spread 0 0 0 1 0 103.00 68.67 34.33 +/-0.35% center spread 0 0 0 1 1 105.00 70.00 35.00 +/-0.35% center spread 0 0 1 0 0 107.00 71.33 35.67 +/-0.35% center spread 0 0 1 0 1 109.00 72.67 36.33 +/-0.35% center spread 0 0 1 1 0 111.00 74.00 37.00 +/-0.35% center spread 0 0 1 1 1 114.00 76.00 38.00 +/-0.35% center spread 0 1 0 0 0 117.00 78.00 39.00 +/-0.35% center spread 0 1 0 0 1 120.00 80.00 40.00 +/-0.35% center spread 0 1 0 1 0 127.00 84.67 42.33 +/-0.35% center spread 0 1 0 1 1 130.00 86.67 43.33 +/-0.35% center spread 0 1 1 0 0 133.33 88.89 44.44 +/-0.35% center spread 0 1 1 0 1 170.00 56.67 28.33 +/-0.35% center spread 0 1 1 1 0 180.00 60.00 30.00 +/-0.35% center spread 0 1 1 1 1 190.00 63.33 31.67 +/-0.35% center spread 1 0 0 0 0 133.90 66.95 33.48 +/-0.35% center spread 1 0 0 0 1 133.33 66.67 33.33 0 to -0.6% down spread 1 0 0 1 0 120.00 60.00 30.00 +/-0.35% center spread 1 0 0 1 1 125.00 62.50 31.25 +/-0.35% center spread 1 0 1 0 0 134.90 67.45 33.73 +/-0.35% center spread 1 0 1 0 1 137.00 68.50 34.25 +/-0.35% center spread 1 0 1 1 0 139.00 69.50 34.75 +/-0.35% center spread 1 0 1 1 1 141.00 70.50 35.25 +/-0.35% center spread 1 1 0 0 0 143.00 71.50 35.75 +/-0.35% center spread 1 1 0 0 1 145.00 72.50 36.25 +/-0.35% center spread 1 1 0 1 0 150.00 75.00 37.5 +/-0.35% center spread 1 1 0 1 1 155.00 77.50 38.75 +/-0.35% center spread 1 1 1 0 0 160.00 80.00 40.00 +/-0.35% center spread 1 1 1 0 1 170.00 85.00 42.50 +/-0.35% center spread 1 1 1 1 0 66.67 66.67 33.34 0 to -0.6% down spread 1 1 1 1 1 200.00 66.67 33.33 0 to -0.6% down spread 0 - Frequency is selected by hardware select, latched inputs 1 - Frequency is selected by Bit 2,7:4 0 - Normal 1 - Spread spectrum enable 0 - Watch dog safe frequency will be selected by latch inputs 1 - Watch dog safe frequency will be programmed by Byte 10 bit (4:0)
Note 1
0 1 0
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
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Integrated Circuit Systems, Inc.
ICS950202
Byte 1: Output Control Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Pin# 40, 39 44, 43 47, 46 -
PWD 1 1 1 X X X X X
Description CPUT/C2 CPUT/C1 CPUT/C0 FS4 Read FS3 Read FS2 Read FS1 Read FS0 Read
b a ck b a ck b a ck b a ck b a ck
Byte 2: Output Control Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin# 17 16 15 12 11 10 9 PWD X 1 1 1 1 1 1 1 Description MULTSEL (Read back) PCICLK_6 PCICLK_5 PCICLK_4 PCICLK_3 PCICLK_2 PCICLK_1 PCICLK_0
Byte 3: Output Control Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Pin# 34 35 31 6 5
PWD 1 1 1 X 0 X 1 1
Description 48MHZ_DOT 48MHz_USB Reset gear shift detect 1 = Enable, 0 = Disable Reserved 3V66_0/VCH_CLK, (default) = 66.66MHz, 1=48MHz Reserved PCICLK8 PCICLK7
Byte 4: Output Control Register (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Pin# 20 31 22 21
PWD X X 1 1 X X 1 1
Description Reserved Reserved 3V 66_1 3V66_0/VCH_CLK Reserved Reserved 3V 66_3 3V 66_2
Notes: 1. PWD = Power on Default 2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC off, and external resistor termination will bring CPUCLKC low.
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Integrated Circuit Systems, Inc.
ICS950202
Byte 5: Programming Edge Rate (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Pin# X X X X X X X X
PWD 0 0 0 0 0 0 0 0
Description (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
Byte 6: Vendor ID Register (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Revision ID Bit3 Revision ID Bit2 Revision ID Bit1 Revision ID Bit0 Vendor ID Bit3 Vendor ID Bit2 Vendor ID Bit1 Vendor ID Bit0
PWD X X X X 0 0 0 1
Description Revision ID values will be based on individual device's revision (Reserved) (Reserved) (Reserved) (Reserved)
Byte 7: Revision ID and Device ID Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Device ID7 Device ID6 Device ID5 Device ID4 Device ID3 Device ID2 Device ID1 Device ID0
PWD Description 0 0 1 Device ID values will be based on individual device 0 "22H" in this case. 0 0 1 0
Byte 8: Byte Count Read Back Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0
PWD Description 0 0 0 Note: Writing to this register will configure byte count and how 0 many bytes will be read back, default is 0FH = 15 bytes. 1 1 1 1
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Integrated Circuit Systems, Inc.
ICS950202
Byte 9: Watchdog Timer Count Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
PWD Description 0 0 0 The decimal representation of these 8 bits correspond to X * 0 290ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 1 8 * 290ms = 2.3 seconds. 0 0 0
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Program Enable WD Enable WD Alarm S F4 S F3 S F2 S F1 S F0
PWD 0 0 0 0 1 0 0 0
Description Programming Enable bit 0 = no programming. Frequencies are selected by HW latches or Byte0 1 = enable all I2C programing. Watchdog Enable bit. This bit will over write WDEN latched value. 0 = disable, 1 = Enable. Watchdog Alarm Status 0 = normal 1= alarm status Watchdog safe frequency bits. Writing to these bits will configure the safe frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Ndiv 8 Mdiv 6 Mdiv 5 Mdiv 4 Mdiv 3 Mdiv 2 Mdiv 1 Mdiv 0
PWD X X X X X X X X
Description N divider bit 8
The decimal respresentation of Mdiv (6:0) corresposd to the reference divider value. Default at power up is equal to the latched inputs selection.
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
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Name Ndiv 7 Ndiv 6 Ndiv 5 Ndiv 4 Ndiv 3 Ndiv 2 Ndiv 1 Ndiv 0
PWD Description X X X The decimal representation of Ndiv (8:0) correspond to the X VCO divider value. Default at power up is equal to the latched inputs selecton. Notice Ndiv 8 is located in Byte 11. X X X X
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Integrated Circuit Systems, Inc.
ICS950202
Byte 13: Spread Spectrum Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name SS 7 SS 6 SS 5 SS 4 SS 3 SS 2 SS 1 SS 0
PWD Description X X The Spread Spectrum (12:0) bit will program the spread X precentage. Spread precent needs to be calculated based on the X VCO frequency, spreading profile, spreading amount and spread X frequency. It is recommended to use ICS software for spread X programming. Default power on is latched FS divider. X X
Byte 14: Spread Spectrum Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Reserved Reserved Reserved SS 12 SS 11 SS 10 SS 9 SS 8
PWD X X X X X X X X
Description Reserved Reserved Reserved Spread Spectrum Bit 12 Spread Spectrum Bit 11 Spread Spectrum Bit 10 Spread Spectrum Bit 9 Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name CPU Div 3 CPU Div 2 CPU Div 1 CPU Div 0 CPU Div 3 CPU Div 2 CPU Div 1 CPU Div 0
PWD 0 1 0 0 0 1 0 0
Description CPU 2 clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider. CPU (1:0) clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider.
Byte 16: Output Divider Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Div 3 Div 2 Div 1 Div 0 Div 3 Div 2 Div 1 Div 0
PWD 0 1 0 1 0 1 0 1
Description 3V66_0 clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider. 3V66 (3:1) clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider.
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Integrated Circuit Systems, Inc.
ICS950202
Byte 17: Output Divider Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name 3V66_INV 3V66_INV CPU_INV CPU_INV
PWD 0 0 0 0
Description 3V66_0 Phase Inversion bit 3V66 (3:1) Phase Inversion bit CPU 2 Phase Inversion bit CPU (1:0) Phase Inversion bit
PCI Div 3 PCI Div 2 PCI Div 1 PCI Div 0
1 0 0 1
PCI clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 2. Default at power up is latched FS divider.
Table 1
Table 2
Div (3:2) Div (1:0) 00 01 10 11
00 /2 /3 /5 /7
01 /4 /6 /10 /14
10 /8 /12 /20 /28
11 /16 /24 /40 /56
Div (3:2) Div (1:0) 00 01 10 11
00 /4 /3 /5 /9
01 /8 /6 /10 /18
10 /16 /12 /20 /36
11 /32 /24 /40 /72
Byte 18: Group Skew Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name CPU_Skew 1 CPU_Skew 0 Reserved Reserved CPU_Skew 1 CPU_Skew 0 Reserved Reserved PWD 0 0 0 0 0 0 0 0 Description These 2 bits delay the CPUCLKC/T2 with respect to CPUCLKC/T (1:0) 00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps Reserved Reserved These 2 bits delay the CPUCLKC/T (1:0) clock with respect to CPUCLKC/T2 00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps Reserved Reserved
Byte 19: Group Skew Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name 3V66_Skew 1 3V66_Skew 0 Reserved Reserved 3V66_Skew 1 3V66_Skew 0 Reserved Reserved
PWD 1 0 0 0 0 1 0 0
Description These 2 bits delay the 3V66 (3:2) with respect to CPUCLK 00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps Reserved Reserved These 2 bits delay the 3V66 (1:0) with respect to CPUCLK 00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps Reserved Reserved
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Integrated Circuit Systems, Inc.
ICS950202
Byte 20: Group Skew Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name PCI_Skew 3 PCI_Skew 2 PCI_Skew 1 PCI_Skew 0 Reserved Reserved Reserved Reserved PWD 1 0 0 0 1 0 0 0 Description These 4 bits can change the CPU to PCI (8:0) skew from 2.2ns 0.7ns. Default at power up is 0.5ns. Each binary increment or decrement of Bits (3:0) will increase or decrease the delay of the PCI clocks by 100ps. Reserved Reserved Reserved Reserved
Byte 21: Slew Rate Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name PCICLK8 Slew 1 PCICLK8 Slew 0 PCICLK7 Slew 1 PCICLK7 Slew 0 3V66 (3:1)_Slew 1 3V66 (3:1)_Slew 1 3V66_0_Slew 1 3V66_0_Slew 0 PWD 1 0 1 0 1 0 1 0 Description PCICLK8 clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak PCICLK7 clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak 3V66 (3:1) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak 3V66_0 clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak
Byte 22: Slew Rate Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name REF Slew 1 REF Slew 0 PCI (6:4) Slew 1 PCI (6:4) Slew 0 PCI (3:1) Slew 1 PCI (3:1) Slew 0 PCI0 Slew 1 PCI0 Slew 0 PWD 1 0 1 0 1 0 1 0 Description REF clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak PCI (6:4) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak PCI (3:1) clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak PCI0 clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak
Byte 23: Slew Rate Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Reserved Reserved VCH Slew 1 VCH Slew 0 48USB Slew 1 48USB Slew 0 48DOT Slew 1 48DOT Slew 0
PWD X X 1 0 1 0 1 0
Description Reserved VCH clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak 48USB clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak 48DOT clock slew rate control bits. 01 = strong: 11 = normal; 10 = weak
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Integrated Circuit Systems, Inc.
ICS950202
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage V DD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL V IH V IL IIH I IL1 Input Low Current I IL2 Operating Supply Current Powerdown Current Input Frequency Input Capacitance Clk Stabilization1 3V66 to PCI
1 1
CONDITIONS
MIN 2 VSS0.3 -5 -5
TYP
MAX VDD+0. 3 0.8 5
UNITS V V mA
IDD3.3OP I DD3.3PD Fi CIN COUT CINX TSTAB tsk 3V66-PCI
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL= Full load IREF= 2.32 V DD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From VDD = 3.3 V to 1% target frequency VT = 1.25 V/ VT = 1.5 V (target) VT = 1.25 V/ VT = 1.5 V (tol)
mA -200 221 22 14.32 360 25 5 6 45 1.8 1.5 2.8 150 3.5 500 mA mA MHz pF pF pF ms ns ps
27
Guarenteed by design,not 100% tested in production
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Integrated Circuit Systems, Inc.
ICS950202
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo1 VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm CONDITIONS VO = Vx Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 200MHz nominal 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V MIN 3000 660 -150 -300 250 770 5 756 -7 350 12 -300 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 4.8735 5.8732 7.3728 9.8720 175 175 850 mV 150 1150 550 140 300 5.0015 5.0266 6.0018 6.0320 7.5023 5.4000 10.0030 10.0533 mV mV mV ppm ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps % ps ps 1 1 1 1 1 1,2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1 1 1 1 1 1 1 TYP MAX UNITS NOTES 1 1
Average period
Tperiod
Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle Skew Jitter, Cycle to cycle
1 2
Tabsmin tr tf d-tr d-tf dt3 tsk3 tjcyc-cyc
332 344 30 30 49 8 60
700 700 125 125 55 100 150
Measurement from differential wavefrom VT = 50% Measurement from differential wavefrom
45
Guaranteed by design, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz
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Integrated Circuit Systems, Inc.
ICS950202
Electrical - Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3V +/-5%; CL= 10- 30pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output Frequency FO Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
MIN 12 2.4
TYP 33.33
MAX 55
UNITS MHz
RDSN1 V OH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1 tjcyc-cyc
VO = VDD*(0.5) IOH = -1mA IOL = -1mA VOH@ MIN =1.0V, V OH@ MAX =3.135V VOL@ MIN = 1.95 V VOL@ MAX = 0.4V V OL = 0.4V, Voh =2.4V VOH = 2.4V, VOL = 0.4V V T = 1.5V V T = 1.5V V T = 1.5V
V V mA
0.17 -33 30 0.5 0.5 45 60 23 1.7 1.4 53.6 218 210
0.55 -33
38 2 2 55 500 250
mA ns ns % ps ps
Guarenteed by design,not 100% tested in production
Electrical Characteristics-3V66
TA = 0 - 70C; VDD = 3.3V+/- 5%; CL= 10-30pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
MIN 12 2.4
TYP 66.66
MAX 55
UNITS MHz
RDSP11 VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tf1 t jcyc-cyc1
VO = VDD*(0.5) I OH = -1mA I OL = -1mA VOH@ MIN =1.0V, VOH@ MAX =3.135V VOL@ MIN = 1.95 V, VOL@ MAX = 0.4V VOL = 0.4V, Voh =2.4V VOH = 2.4V, VOL = 0.4V VT = 1.5V VT = 1.5V VT = 1.5V
V V mA
0.17 -33 30 0.5 0.5 45 45 60 23 1.7 1.4 50.7 284 170
0.55 -33
38 2 2 55 500 250
mA ns ns % ps ps
Guarenteed by design,not 100% tested in production
0461L--05/28/03
14
Integrated Circuit Systems, Inc.
ICS950202
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70C; VDD = 3.3V +/-5%; CL= 10-30pF (unlessotherwise stated) PARAMETER SYMBOL CONDITIONS VO = VDD*(0.5) Output Frequency FO Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current 48DOT Rise Time 48DOT Fall Time Duty Cycle-48 DOT VCH 48 USB -Rise Time VCH 48 USB -Fall Time Duty Cycle-48 USB 48 DOT to 48 USB Skew RDSN1 1 VOH1 VOL1 IOH1 VO = VDD*(0.5) IOH = -1mA IOL = -1mA VOH@ MIN =1.0V VOH@ MAX =3.135V VOL@ MIN = 1.95 V IOL1 tr1 tf1 dt1
1 1 1
MIN 12 2.4 -29 29 0.5 0.5 45 1 1 45
TYP 48.008 3.1 0.19 -42 -6 56 24 0.93 0.81 52.4 1.7 1.4 52.9 187 207
MAX 55 0.55 -23 27 1 1 55 2 2 55 1 350
UNITS MHz
V V mA mA ns ns % ns ns % ns ps
VOL@ MAX = 0.4V VOL = 0.4V, Voh =2.4V VOH = 2.4V, VOL = 0.4V VT = 1.5V VOL = 0.4V, Voh =2.4V VOH = 2.4V, VOL = 0.4V VT = 1.5V VT = 1.5V
1
t r1 tf1 dt11 t skew1
Jitter tjcyc-cyc 1Guarenteed by design, not 100% tested.
VT = 1.5V
Electrical Characteristics- REF
TA = 0 - 70C; VDD = 3.3V+/- 5%; CL= 10-30pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
MIN 20 2.4
TYP 14.318
MAX 60
UNITS MHz
RDSP11 VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tjcyc-cyc1
V O = VDD*(0.5) IOH = -1mA IOL = -1mA VOH@ MIN =1.0V, V OH@ MAX =3.135V VOL@ MIN = 1.95 V VOL@ MAX = 0.4V VOL = 0.4V, Voh =2.4V VOH = 2.4V, V OL = 0.4V VT = 1.5V VT = 1.5V
V V mA
0.17 -33 30 1 1 45 60 23 1.7 1.4 54.5 400
0.55 -33
38 2 2 55 1000
mA ns ns % ps
Guarenteed by design,not 100% tested in production
0461L--05/28/03
15
Integrated Circuit Systems, Inc.
ICS950202
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
0461L--05/28/03
16
Integrated Circuit Systems, Inc.
ICS950202
3V66 & PCI Phase Relationship All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci.
3V66 (1:0) 3V66 (4:2) 3V66_5 PCICLK_F (2:0) PCICLK (6:0) Tpci
Group Skews at Common Transition Edges
GROUP 3V66 PCI 3V66 to PCI
1
SYMBOL CONDITIONS 3V66 3V66 (5:0) pin to pin skew PCI S3V66-PCI PCI_F (2:0) and PCI (6:0) pin to pin skew 3V66 (5:0) leads 33MHz PCI
MIN 0 0 1.5
TYP
MAX UNITS 500 ps 500 3.5 ps ns
Guarenteed by design, not 100% tested in production.
PD# Functionality
CPU_STOP# 1 0
CPUT Normal iref * Mult
CPUC Normal Float
3V66 66MHz Low
66MHz_OUT 66MHz_IN Low
PCICLK_F PCICLK 66MHz_IN Low
PCICLK 66MHz_IN Low
USB/DOT 48MHz 48MHz Low
0461L--05/28/03
17
Integrated Circuit Systems, Inc.
ICS950202
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge. Assertion of PCI_STOP# Waveforms
PCI_STOP# PCI_F[2:0] 33MHz PCI[6:0] 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven. Assertion of CPU_STOP# Waveforms
CPU_STOP# CPUT CPUC
CPU_STOP# Functionality
CPU_STOP# 1 0
CPUT Normal iref * Mult
CPUC Normal Float
0461L--05/28/03
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Integrated Circuit Systems, Inc.
ICS950202
N
c
SYMBOL
L
INDEX AREA
E1
E
12 D h x 45
a
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS950202yFT
Example:
ICS XXXX y F - T
Designation for tape and reel packaging Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS, AV = Standard Device
0461L--05/28/03
19

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